| Dir : /lib/firmware/cirrus/ |
| Server: Linux tamarillo.o2switch.net 4.18.0-553.33.1.lve.el8.x86_64 #1 SMP Tue Dec 24 22:25:00 UTC 2024 x86_64 IP: 109.234.166.180 |
| Dir : //lib/firmware/cirrus/cs35l63-a1-dsp1-misc-17aa2352.wmfw |
WMFW( 7 � $ C�nh �, Wed 09 Jul 2025 15:57:07 GMT Daylight Time � � d ' � � �� ( � 5 �> � . f �& � � F �f H Z $�8 ~ � �9 Y ~ � � � �
| 8 � �
� �
� 0 � 0
� � + � M � � d � � j ( � �
4 �
" �
; �! )
W b � � �$
B� �&� R �( � �" b �) � �#V �* '
� B� �3 � � �4
� �1 ? �0T 0 �5 O �7� J �/ 2 7 � �ޭ� U � 4 � � � ROw !O� �� �@ � =aO� =���@ P�@
� P
�� ��H4��H D� �� a�� �!К@�� @
� �
�
�֙!�H�H���u�t�@t�@�H� H�a�@���@՚@�H�@��g��z�� ՙ � R SR��mٙ P� � l _q{��q�� � �!� P !O� n �� �@ @ ��@� � �O ���� �@�@� #0 �Y@ P� � Z�"�Fn s�� �� �@ z�� � � �@ � ����� AO� }� ���@ � � �� � �� ����@b� ��� ��O f� � �� ���!� YQO���)� n� � �!�@�� I��A�D@ # i� @� Ȅ �@�{�� G�� �@� ,��D�� � � {���Ȝ�@� m�ِ� �@��X�ڐ�c�� AO� Ȅ�@ҙ �@O� {� �@��Ě � � �� {��G� ��@�� �)� � �� � ��� �D)� �� � ����O � �� ����� a�� � ,����a� �)1��@ @^ny� ��p � ��� P �O� ~� � �@-� n �� ��ɚ � �� =��_�
)p
Q�QO� O`�_� ��a��_;B U��� � ��� � �ʙ � f� �� �O� �� @�)� �� %2 �)��9� I�� � ����k�O���A �� �� ! � ��� � � ᱱ� ��!�@O !�� � �� �@� 1� n �� � O��_�f�� � /й���� ^ �u�r
) ��_Q��
_4)�1�i� i� O��_A.nb�a��_� RQ_8 �I�� � ����� P�� ��� ��%�@n�@ ��@�$���mf�
0��� �J�aJi V�0�� �Ah�i Vh0�� �AV�i �Ah0� �V�i���h0 � @ �� 0P#�0 � � H�
�p ' �F� �Q�0P m � � H� �P0 %!0�F� �0p � M��@� �����_� �8 ��R�@ �� @ �䏬�� � �I��� O�*� *� �Ix� ��O�I� � � *�I*� @���� `�����B��@� 0F�� ( � �� ��� ��K��� O �����@ � �� � ! � p� @ ���� �� � � ��@ � � I� ��*�
n Q �� � ��� �� A n� � �� ���� ! P �� �� � O��� � � � � ����Й �� P� *��H�� �� �@ )� � � '\� ,I0 ��O�O� @` � q n� I� ���Iِ � -I xI��0 q��@ � � @ m �Oə � ��@� !O� ��� �� p �� p� � � �� NJ ����@ � Б��_�_� 1�Q� /3�
P
&�` 6� ? 0 v�p A_� _����@�� �@�
��� �"� O �� ��A�@ � � ` ���@ �� �
� �� ! �耠 �@ �*�0"A�� %l� �
!�@� 1O � ���@�4�0��
�0
��� ٰ �$L 8�ٰ ȸ4踆��L�1� !�1ȸFY@L H Ћえ�` �d��a�d���p� ����
�ꆆ� O ��m��B������@I@m YT����@ )�%��&�$b���_`�~�i����n�~�a\� ���l�� ��#�a����ʠ � +s ���Ɂ� v 0 � % @
0��Q�0� �� �%� �>֏@ � oѪ�;!���� 0�@ \��֞ � ����� m�#ѷ��� ����� eO� �� 9����@�dI �K��!��S �A��@ !i
(i
z��f�%�� 7����� v+ � %0 !i
(7�f��� {�%m��� �l�ёTO�Tx�!a�%e
XP �'5 �� ��'l�1� U�a � � ~��
%Q \S �� � oѪ����� v�d�\ �֠ ������ m��"
i��� ����� eO���DP��X%H�� | �
( ��!i�%o�����v� 0�@ � �
( ��!i�%o�����@mv�T��@�!aO�e����% � �e� � �
@�$n��%H%��(��� I� �I&���� �� �� J � &��
� � ��� II�H�� � %h.�� ��, � ��@ �!�Uq�T����@�%� I�( ފ���� � % ��I�� � �� � % �
������ I� � %���� h.��@ �.A��h� PC��叁 �|�@,�F��A�L������l�M�y���N�5�L�်�� 2 �
R ��1���� � � �%M�9O�� (��Sh�&��������h �r���%���J(m� � v�x����(@a���� x�%�m� ���&(��UH��� ������h�r�(m%���J�@[� v� T@x����( a�%��x��m � �EO�T �0�@ h� ��F Em�����'Q�d}��A���r%$�9�XaI%k����h �h
�(>��\m mn�!D������I�k���� a�%� ���"���P$�� ������h�r�(m%���J�@[� v T�� d����iaK��� �%�`O ��P ��q�@hm �Ҁ E��Ȝ��'a�i)�%q����G$�y&��i�� ��]� �m����(h�\h
m>��!m ��n�DY���r��'� ��@ �� (��&�������h �r���%���J(m@[� v�T� �(@xx�x�� �� �Qh
��h�H8C�� ����&������(9h
Fr�F�,X��X`m�� v�x��� (Ie��َ! �m� �8��&�����(�h
F��F�9X�rX`m,[��v�@��� T(Ix��� �!em�OኀP�`J��@ �q��h m ���@� �D � FIRMWARE_CS35L63 4 FW_HL_STT FIRMWARE_CS35L63_HALO_STATE <
FW_HL_HARTBAT FIRMWARE_CS35L63_HALO_HEARTBEAT <
FW_ADO_BLK_SZ FIRMWARE_CS35L63_AUDIO_BLK_SIZE � 8 FW_RFCLK_SRC FIRMWARE_CS35L63_REFCLK_SRC � D FW_PLL_RFCLK_FRQ FIRMWARE_CS35L63_PLL_REFCLK_FREQ �
D
FW_PLL_F_MCLK %FIRMWARE_CS35L63_REFCLK_PLL_FREQ_MCLK 8 FW_BOT_RASN FIRMWARE_CS35L63_BOOT_REASON � @
FW_REFCLK_DET "FIRMWARE_CS35L63_REFCLK_DETECT_32K � < FW_HW_CLCK_STT FIRMWARE_CS35L63_HW_CLOCK_STATE � @ FW_CP_MTR_ENBL !FIRMWARE_CS35L63_CPU_METER_ENABLE � D FW_MPS_OVRRN_FLG "FIRMWARE_CS35L63_MIPS_OVERRUN_FLAG � D FW_MIPS_OR_HBN $FIRMWARE_CS35L63_MIPS_OVERRUN_HB_NUM � H FW_DPLL_DB_T *FIRMWARE_CS35L63_DPLL_UNLOCK_DEBOUNCE_TYPE � H FW_DPLL_DB_CNT +FIRMWARE_CS35L63_DPLL_UNLOCK_DEBOUNCE_COUNT � 4 FW_TN_TKN FIRMWARE_CS35L63_TUNE_TOKEN � �
EVENT_HANDLER � � GPIO � � MAILBOX ,
QUEUE_BASE MAILBOX_QUEUE_BASE , QUEUE_LEN MAILBOX_QUEUE_LEN , QUEUE_WT MAILBOX_QUEUE_WT , QUEUE_RD MAILBOX_QUEUE_RD $ STATUS MAILBOX_STATUS �8 � PM < PM_TIMEOUT_TICKS PM_PM_TIMER_TIMEOUT_TICKS � , PM_CUR_STATE PM_PM_CUR_STATE 4
PM_PWR_ON_SEQ PM_POWER_ON_SEQUENCE � � 0 ACTIVE_SEQUENCEPM_ACTIVE_SEQUENCE �� � 4 STANDBY_SEQUENCE PM_STANDBY_SEQUENCE �� � � AUDIO_SYSTEM 4
AS_ADO_STT AUDIO_SYSTEM_AUDIO_STATE � 0
AS_LST_CMD AUDIO_SYSTEM_LAST_CMD � D AS_STA_2_SYD &AUDIO_SYSTEM_STRM_ACTIVE_TO_SYNTH_DONE � H AS_SYA_2_STA *AUDIO_SYSTEM_SYNTH_ACTIVE_TO_STREAM_ACTIVE �
D AS_PLL_RESYNC_R&AUDIO_SYSTEM_AMP_PLL_UNLOCK_RESYNC_REQ � H AS_STA_2_SYA *AUDIO_SYSTEM_STREAM_ACTIVE_TO_SYNTH_ACTIVE � ( AS_ERRRAUDIO_SYSTEM_ERROR � 8
AS_PAK_CP_LAD AUDIO_SYSTEM_PEAK_CPU_LOAD � < AS_CRRNT_CP_LAD AUDIO_SYSTEM_CURRENT_CPU_LOAD � @ AS_SYNTHSS_ENBLD AUDIO_SYSTEM_SYNTHESIS_ENABLED � " 4 AS_ADO_STTSAUDIO_SYSTEM_AUDIO_STATUS � # 0 AS_PRJCT_IDAUDIO_SYSTEM_PROJECT_ID $ 0 AS_CHNNL_IDAUDIO_SYSTEM_CHANNEL_ID % 8 AS_SNPSHT_ID AUDIO_SYSTEM_SNAPSHOT_ID � � MDSYNC �p �
ULTRASONIC � P
ULTRASONIC_EN 3ULTRASONIC_ULTRASONIC_CTRL_STRUCT_ULTRASONIC_ENABLE � � � PROTECT_LITE . < CAL_R_EXPECTED PROTECT_LITE_R_CALIB_0_R_REF < CAL_R_DELTA"PROTECT_LITE_R_CALIB_0_R_DELTA_MAX � LCHIRP_CUR_FREQhPROTECT_LITE_DIAGNOSTICS_STRUCT_0_CALIBRATION_AND_DIAGNOSTICS_RX_CMPST_0_LINEARCHIRP_0_CURRENT_FREQUENCY | LCHIRP_FSTOP \PROTECT_LITE_DIAGNOSTICS_STRUCT_0_CALIBRATION_AND_DIAGNOSTICS_RX_CMPST_0_LINEARCHIRP_0_FSTOP |
LCHIRP_AMP `PROTECT_LITE_DIAGNOSTICS_STRUCT_0_CALIBRATION_AND_DIAGNOSTICS_RX_CMPST_0_LINEARCHIRP_0_AMPLITUDE C T CALI_TUNE_APP_EN 2PROTECT_LITE_SMART_CALIBRATION_APPROVE_TUNE_ENABLE D T CALI_NORM_EN 4PROTECT_LITE_SMART_CALIBRATION_NORMALIZE_REDC_ENABLE E L CALI_TEMP_OFFSET *PROTECT_LITE_SMART_CALIBRATION_TEMP_OFFSET F T CALI_MIN_EST_TMP 3PROTECT_LITE_SMART_CALIBRATION_MIN_EST_AMBIENT_TEMP G T CALI_MAX_EST_TMP 3PROTECT_LITE_SMART_CALIBRATION_MAX_EST_AMBIENT_TEMP P PROTECT_LITE_EN2PROTECT_LITE_PROTECT_LITE_CTRL_PROTECT_LITE_ENABLE H CAL_EN 1PROTECT_LITE_PROTECT_LITE_CTRL_CALIBRATION_ENABLE H DIAG_EN1PROTECT_LITE_PROTECT_LITE_CTRL_DIAGNOSTICS_ENABLE L CAL_CHECKSUM ,PROTECT_LITE_VAR_ARRAY_CHECK_SUM_CALIBRATION � H
CAL_STATUS /PROTECT_LITE_VAR_ARRAY_IMPEDANCE_MEASURE_STATUS � L CAL_R 5PROTECT_LITE_VAR_ARRAY_MEASURED_IMPEDANCE_CALIBRATION � P CAL_SET_STATUS 3PROTECT_LITE_VAR_ARRAY_IMPEDANCE_THRESH_CALC_STATUS L CAL_R_SELECTED -PROTECT_LITE_VAR_ARRAY_INITIAL_CALI_IMPEDANCE L TEMP_COIL_RATE /PROTECT_LITE_VAR_ARRAY_RATE_OF_COIL_TEMP_CHANGE � H TEMP_EST_COR )PROTECT_LITE_VAR_ARRAY_TEMP_EST_CORRECTED �
H TEMP_COIL_C.PROTECT_LITE_VAR_ARRAY_TEMP_MEASURED_CORRECTED � L FIX_MOD_MAX_EXC.PROTECT_LITE_VAR_ARRAY_FIX_MODEL_MAX_EXCURSION � L
DD_MAX_EXC 0PROTECT_LITE_VAR_ARRAY_DIRECT_DISP_MAX_EXCURSION � P OVERS_REACT_GAIN .PROTECT_LITE_VAR_ARRAY_OVERSIGHT_REACTION_GAIN � < TONE_FLAG PROTECT_LITE_VAR_ARRAY_TONE_FLAG � P MAX_EXC_BEFO_LIM /PROTECT_LITE_VAR_ARRAY_MAX_EXCUR_BEFORE_LIMITER � T
EXC_AFTER_LIM 4PROTECT_LITE_VAR_ARRAY_MAX_EXCUR_VALUE_AFTER_LIMITER � D EXCUR_GAIN_MAX %PROTECT_LITE_VAR_ARRAY_EXCUR_GAIN_MAX � X THERM_OVER_ACT_I 4PROTECT_LITE_VAR_ARRAY_THERM_OVERRIDE_ACTIVATION_IND � P THERM_R_ATT_MIN3PROTECT_LITE_VAR_ARRAY_THERMAL_RATE_ATTENUATION_MIN � L THERM_ATTEN_MIN.PROTECT_LITE_VAR_ARRAY_THERMAL_ATTENUATION_MIN � T CB_THERM_ATT_MIN 3PROTECT_LITE_VAR_ARRAY_COMB_THERMAL_ATTENUATION_MIN � L EXC_GAIN_DIG2MM,PROTECT_LITE_VAR_ARRAY_EXCURSION_GAIN_DIG2MM � H
EXC_OFFSET_MM *PROTECT_LITE_VAR_ARRAY_EXCURSION_OFFSET_MM � ( D
TEMP_COIL_EST $PROTECT_LITE_VAR_ARRAY_TEMP_COIL_EST B T CAL_AMBIENT9PROTECT_LITE_CALIB_DIAG_VAR_ARRAY_CAL_AMBIENT_TEMPERATURE � C D DIAG_F0,PROTECT_LITE_CALIB_DIAG_VAR_ARRAY_Z_CURVE_F0 D X DIAG_F0_STATUS 9PROTECT_LITE_CALIB_DIAG_VAR_ARRAY_Z_CURVE_ANALYSIS_STATUS F d CAL_IMP_MEAS_CAL @PROTECT_LITE_CALIB_DIAG_VAR_ARRAY_MEASURED_IMPEDANCE_CALIBRATION G D CAL_R_OUT +PROTECT_LITE_CALIB_DIAG_VAR_ARRAY_CAL_R_OUT K T DIAG_Z_LOW_DIFF6PROTECT_LITE_CALIB_DIAG_VAR_ARRAY_DIAGNOSTICS_LOW_DIFF L L CAL_RE_EST_GAIN-PROTECT_LITE_CALIB_DIAG_VAR_ARRAY_RE_EST_GAIN M P
CAL_ALPHA_REF 1PROTECT_LITE_CALIB_DIAG_VAR_ARRAY_ALPHA_REFERENCE N H
CAL_TC0_CALIB +PROTECT_LITE_CALIB_DIAG_VAR_ARRAY_TC0_CALIB V P CAL_ZCURVE_F_LOW /PROTECT_LITE_CALIB_DIAG_VAR_ARRAY_Z_CURVE_F_LOW Y \ CALI_EST_AMB_TMP 9PROTECT_LITE_SMART_CALIB_VAR_ARRAY_ESTIMATED_AMBIENT_TEMP � 8� PEQ20_1 L PEQ20_1_ENABLE ,PEQ20_1_PEQ20_PEQ20_CTRL_STRUCT_PEQ20_ENABLE � H PEQ20_1_FILTERS)PEQ20_1_PEQ20_PEQ20_FILTERBANK_PEQ20_BAND � � 9� PEQ20_2 L PEQ20_2_ENABLE ,PEQ20_2_PEQ20_PEQ20_CTRL_STRUCT_PEQ20_ENABLE � H PEQ20_2_FILTERS)PEQ20_2_PEQ20_PEQ20_FILTERBANK_PEQ20_BAND � �L � MBDRC / T M_DRC1_LD_OP_LVL 0MBDRC_DRC_1_STRUCT_DRC_LEVEL_DETECT_OUTPUT_LEVEL � O @
M_DRC1_OP_LVL #MBDRC_DRC_1_STRUCT_DRC_OUTPUT_LEVEL � T T M_DRC2_LD_OP_LVL 0MBDRC_DRC_2_STRUCT_DRC_LEVEL_DETECT_OUTPUT_LEVEL � t @
M_DRC2_OP_LVL #MBDRC_DRC_2_STRUCT_DRC_OUTPUT_LEVEL � y T M_DRC3_LD_OP_LVL 0MBDRC_DRC_3_STRUCT_DRC_LEVEL_DETECT_OUTPUT_LEVEL � � @
M_DRC3_OP_LVL #MBDRC_DRC_3_STRUCT_DRC_OUTPUT_LEVEL � � D MBDRC_ENABLE $MBDRC_MBDRC_CTRL_STRUCT_MBDRC_ENABLE � � � INPUT_CONDITIONER T IC_EN ?INPUT_CONDITIONER_INPUT_CONDITIONER_CTRL_STRUCT_INP_COND_ENABLE � \ IC_CH_BAL AINPUT_CONDITIONER_INPUT_CONDITIONER_CTRL_STRUCT_INP_COND_CHAN_BAL � d IC_CH_BALSMHINPUT_CONDITIONER_INPUT_CONDITIONER_CTRL_STRUCT_INP_COND_CHAN_BAL_SMOOTH � h IC_MM_XO_ENMINPUT_CONDITIONER_INPUT_CONDITIONER_CTRL_STRUCT_INP_COND_MONOMIX_XOVER_ENABLE � d
IC_H_XO_EN JINPUT_CONDITIONER_INPUT_CONDITIONER_CTRL_STRUCT_INP_COND_HALF_XOVER_ENABLE � / h IC_PPU_H_XO_BALKINPUT_CONDITIONER_INPUT_CONDITIONER_PPU_CTRL_STRUCT_INP_COND_HALF_XOVER_BAL � �\ � ACTISONIC � < ACTISONIC_ENABLE ACTISONIC_ACTISONIC_ENABLE � � � LIMITER T LI_DRC_LD_OP_LVL 2LIMITER_DRC_1_STRUCT_DRC_LEVEL_DETECT_OUTPUT_LEVEL � ! D
LI_DRC_OP_LVL %LIMITER_DRC_1_STRUCT_DRC_OUTPUT_LEVEL � & D LI_ENABLE *LIMITER_LIMITER_CTRL_STRUCT_LIMITER_ENABLE � �0 �
INPUT_ENHANCE \ IE_DRC_LD_OP_LVL 8INPUT_ENHANCE_DRC_1_STRUCT_DRC_LEVEL_DETECT_OUTPUT_LEVEL � & H
IE_DRC_OP_LVL +INPUT_ENHANCE_DRC_1_STRUCT_DRC_OUTPUT_LEVEL � + X IE_ENABLE <INPUT_ENHANCE_INPUT_ENHANCE_CTRL_STRUCT_INPUT_ENHANCE_ENABLE � � � NOISEGATE X NG_DRC_LD_OP_LVL 4NOISEGATE_DRC_1_STRUCT_DRC_LEVEL_DETECT_OUTPUT_LEVEL � ! D
NG_DRC_OP_LVL 'NOISEGATE_DRC_1_STRUCT_DRC_OUTPUT_LEVEL � & L NG_ENABLE 2NOISEGATE_NOISE_GATE_CTRL_STRUCT_NOISE_GATE_ENABLE � �T � VIRTUAL_SUB J 4 VS_ENBL VIRTUAL_SUB_VIRTUAL_SUB_ENABLE � � � PDL
� 0 PDL_0_ENABLE PDL_PDL_0_ENABLE � 0 PDL_1_ENABLE PDL_PDL_1_ENABLE � 8 PDL_0_HI_FR PDL_PDL_0_VARS_HI_FULL_RATIO � <
PDL_0_PTHRESH PDL_PDL_0_VARS_PIANO_THRESHOLD � @
PDL_0_PATTNTN PDL_PDL_0_VARS_PIANO_ATTENUATION � @
PDL_0_PBNDSIG PDL_PDL_0_VARS_PIANO_BAND_SIGNAL � 8 PDL_1_HI_FR PDL_PDL_1_VARS_HI_FULL_RATIO � <
PDL_1_PTHRESH PDL_PDL_1_VARS_PIANO_THRESHOLD � @
PDL_1_PATTNTN PDL_PDL_1_VARS_PIANO_ATTENUATION � @
PDL_1_PBNDSIG PDL_PDL_1_VARS_PIANO_BAND_SIGNAL � � PICL � � LOGGER $ ENABLE
LOGGER_ENABLE � $ STATE LOGGER_STATE � $ COUNT LOGGER_COUNT � 8 FRMPRWIN LOGGER_FRAMESPERCAPTUREWINDOW � 4
LOGGER_VAR LOGGER_VARIABLE_VARIABLE �< @ LOGGER_VAR_TYPES LOGGER_VARIABLE_VARIABLE_TYPES � DATA LOGGER_DATA �x � � CLIP_DETECT � � THRESHOLD_LOGGER , ENABLE THRESHOLD_LOGGER_ENABLE � 4 MAX_TEMP THRESHOLD_LOGGER_MAX_TEMP � < THRE_LOG_MAX_EXC THRESHOLD_LOGGER_MAX_EXC @ OVER_TEMP_COUNT THRESHOLD_LOGGER_OVER_TEMP_COUNT � < OVER_EXC_COUNT THRESHOLD_LOGGER_OVER_EXC_COUNT � <
ABNORMAL_MUTE THRESHOLD_LOGGER_ABNORMAL_MUTE � �@ !� PPU (
PPU_ENABLE PPU_PPU_ENABLE � � � BASS_EXTENSION , ENABLE BASS_EXTENSION_ENABLE � L B_EXT_MXSHLFGAIN *BASS_EXTENSION_BASS_EXTENSION_MAXSHELFGAIN �
P
BASS_EXT_GAIN 0BASS_EXTENSION_BASS_EXT_VARS_BASS_EXTENSION_GAIN � �8 $� SDL ENABLE
SDL_ENABLE � � &�
SECURE_ACCESS �P (� TONE_ATTENUATOR , ENABLE TONE_ATTENUATOR_ENABLE � �0 "� SDCA H FU21_MR_US_MU_CU 'SDCA_FU21_MAIN_RENDER_USER_MUTE_CURRENT H FU21_MR_US_MU_NE $SDCA_FU21_MAIN_RENDER_USER_MUTE_NEXT �
L FU21_MR_US_VO_CU )SDCA_FU21_MAIN_RENDER_USER_VOLUME_CURRENT H FU21_MR_US_VO_NE &SDCA_FU21_MAIN_RENDER_USER_VOLUME_NEXT � H PPU21_MA_PO_NU_C &SDCA_PPU21_MAIN_POSTURE_NUMBER_CURRENT D PPU21_MA_PO_NU_N #SDCA_PPU21_MAIN_POSTURE_NUMBER_NEXT � & < SAPU29_PROT_MODE SDCA_SAPU29_PROTECTION_MODE ' @ SAPU29_PROTEC_ST SDCA_SAPU29_PROTECTION_STATUS - < XU22_MR_BYPASS SDCA_XU22_MAIN_RENDER_BYPASS � 0 4 XU22_FDL_STATUSSDCA_XU22_FDL_STATUS � 1 8 XU22_FDL_SET_IND SDCA_XU22_FDL_SET_INDEX � 2 < XU22_FDL_HOS_REQ SDCA_XU22_FDL_HOST_REQUEST � 3 @ XU24_SPK_SNS_BYP SDCA_XU24_SPEAKER_SENSE_BYPASS � < D PDE23_TRD_REQ_PS "SDCA_PDE23_TRANSDUCER_REQUESTED_PS � = @ PDE23_TRD_ACT_PS SDCA_PDE23_TRANSDUCER_ACTUAL_PS � > 8 TG23_TONE_DIVIDE SDCA_TG23_TONE_DIVIDER ^ @ XU22_FDL_MES_OFF SDCA_XU22_FDL_MESSAGE_OFFSET � ` @ XU22_FDL_MES_LEN SDCA_XU22_FDL_MESSAGE_LENGTH � � )� WRITE_DETECT � #� EVENT_LOGGER < EVLOG_HEADER EVENT_LOGGER_EVENT_LOG_HEADER � 0 EVLOG_EN EVENT_LOGGER_ENABLED � 8
BUFFER_STATUS EVENT_LOGGER_BUFFER_STATUS � @ EVLOG_ST_OFF EVENT_LOGGER_START_STREAM_OFFSET � 8 WAS_DISABLED EVENT_LOGGER_WAS_DISABLED �
< EVLOG_TS_SHIFT EVENT_LOGGER_TIMESTAMP_SHIFT � �X *� ASP_MIXER 8 ASP_MIX_ENABLE ASP_MIXER_ASP_MIX_ENABLE � �\ B SHORT_DETECT 8 SHORT_DETECTED SHORT_DETECT_SHORT_DETECTED � �� 3� VMON_SYNTHESIS , ENABLE VMON_SYNTHESIS_ENABLE � P VMS_AC_MOD_IMAX3VMON_SYNTHESIS_ANALOG_CLIPPING_MODULATION_INDEX_MAX � P VMS_AC_INT_R 0VMON_SYNTHESIS_ANALOG_CLIPPING_INTERNAL_RESISTOR � P VMS_AC_EXT_R 0VMON_SYNTHESIS_ANALOG_CLIPPING_EXTERNAL_RESISTOR � L
VMS_AC_LOAD_R ,VMON_SYNTHESIS_ANALOG_CLIPPING_LOAD_RESISTOR � L VMS_IMC_CAL_ST .VMON_SYNTHESIS_IMON_CALIBRATION_IMON_CAL_STATE � P VMS_IMC_CAL_LN 2VMON_SYNTHESIS_IMON_CALIBRATION_CALIBRATION_LENGTH � P VMS_IMC_COR_MAX3VMON_SYNTHESIS_IMON_CALIBRATION_IMON_CORRECTION_MAX � L VMS_IMC_APT_RATE *VMON_SYNTHESIS_IMON_CALIBRATION_ADAPT_RATE � ` VMS_IMC_SINE_THR >VMON_SYNTHESIS_IMON_CALIBRATION_SINEGENERATORSENSE_0_THRESHOLD � P VMS_IMC_IMON_COR /VMON_SYNTHESIS_IMON_CALIBRATION_IMON_CORRECTION � 8 VMON_SCALING VMON_SYNTHESIS_VMON_SCALING � 8 IMON_SCALING VMON_SYNTHESIS_IMON_SCALING � @ ERROR_VOL_ATTACK VMON_SYNTHESIS_ERROR_VOL_ATTACK � @ VMS_ERR_VOL_RLS VMON_SYNTHESIS_ERROR_VOL_RELEASE �� 4� BOOT_BEEP < BOOT_BEEP_ENABLE BOOT_BEEP_BOOT_BEEP_ENABLE � 4
DSP_BEEP_FREQ BOOT_BEEP_DSP_BEEP_FREQ � 8 DSP_BEEP_LEVEL BOOT_BEEP_DSP_BEEP_LEVEL � 8 BB_DSP_BEEP_DURBOOT_BEEP_DSP_BEEP_DURATION � 8 GPIO_BEEP_FREQ BOOT_BEEP_GPIO_BEEP_FREQ � 8 GPIO_BEEP_LEVELBOOT_BEEP_GPIO_BEEP_LEVEL � 4 BEEP_PENDING BOOT_BEEP_BEEP_PENDING � � 1�
TWEETER_XOVER �8 0� TWEETER_LIMITER \ TLI_DRC_LD_OP_LV :TWEETER_LIMITER_DRC_1_STRUCT_DRC_LEVEL_DETECT_OUTPUT_LEVEL � ! L TLI_DRC_OP_LVL -TWEETER_LIMITER_DRC_1_STRUCT_DRC_OUTPUT_LEVEL � & \
TLI_ENABLE BTWEETER_LIMITER_TWEETER_LIMITER_CTRL_STRUCT_TWEETER_LIMITER_ENABLE � � 5� TWEETER_ENHANCE �< 7� SWDE H ( SWDE_ENSWDE_SWDE_ENABLE ,
SWDE_SW_EN SWDE_SWDE_SW_ENABLE ,
SWDE_DE_EN SWDE_SWDE_DE_ENABLE 8 SWDE_SW_M_F1_B0SWDE_ST_WIDE_MID_FILT_1_B0 8 SWDE_SW_M_F1_B1SWDE_ST_WIDE_MID_FILT_1_B1 8 SWDE_SW_M_F1_B2SWDE_ST_WIDE_MID_FILT_1_B2 < SWDE_SW_M_F1_MA1 SWDE_ST_WIDE_MID_FILT_1_MA1 < SWDE_SW_M_F1_MA2 SWDE_ST_WIDE_MID_FILT_1_MA2 8 SWDE_SW_M_F2_B0SWDE_ST_WIDE_MID_FILT_2_B0 8 SWDE_SW_M_F2_B1SWDE_ST_WIDE_MID_FILT_2_B1
8 SWDE_SW_M_F2_B2SWDE_ST_WIDE_MID_FILT_2_B2 < SWDE_SW_M_F2_MA1 SWDE_ST_WIDE_MID_FILT_2_MA1 < SWDE_SW_M_F2_MA2 SWDE_ST_WIDE_MID_FILT_2_MA2
8 SWDE_SW_M_F3_B0SWDE_ST_WIDE_MID_FILT_3_B0 8 SWDE_SW_M_F3_B1SWDE_ST_WIDE_MID_FILT_3_B1 8 SWDE_SW_M_F3_B2SWDE_ST_WIDE_MID_FILT_3_B2 < SWDE_SW_M_F3_MA1 SWDE_ST_WIDE_MID_FILT_3_MA1 < SWDE_SW_M_F3_MA2 SWDE_ST_WIDE_MID_FILT_3_MA2 8 SWDE_SW_S_F1_B0SWDE_ST_WIDE_SIDE_FILT_1_B0 8 SWDE_SW_S_F1_B1SWDE_ST_WIDE_SIDE_FILT_1_B1 8 SWDE_SW_S_F1_B2SWDE_ST_WIDE_SIDE_FILT_1_B2 @ SWDE_SW_S_F1_MA1 SWDE_ST_WIDE_SIDE_FILT_1_MA1 @ SWDE_SW_S_F1_MA2 SWDE_ST_WIDE_SIDE_FILT_1_MA2 8 SWDE_SW_S_F2_B0SWDE_ST_WIDE_SIDE_FILT_2_B0 8 SWDE_SW_S_F2_B1SWDE_ST_WIDE_SIDE_FILT_2_B1 8 SWDE_SW_S_F2_B2SWDE_ST_WIDE_SIDE_FILT_2_B2 @ SWDE_SW_S_F2_MA1 SWDE_ST_WIDE_SIDE_FILT_2_MA1 @ SWDE_SW_S_F2_MA2 SWDE_ST_WIDE_SIDE_FILT_2_MA2 8 SWDE_SW_S_F3_B0SWDE_ST_WIDE_SIDE_FILT_3_B0 8 SWDE_SW_S_F3_B1SWDE_ST_WIDE_SIDE_FILT_3_B1 8 SWDE_SW_S_F3_B2SWDE_ST_WIDE_SIDE_FILT_3_B2 @ SWDE_SW_S_F3_MA1 SWDE_ST_WIDE_SIDE_FILT_3_MA1 @ SWDE_SW_S_F3_MA2 SWDE_ST_WIDE_SIDE_FILT_3_MA2 ! 4 SWDE_SW_M_SCALESWDE_ST_WIDE_MID_SCALE " 4 SWDE_SW_M_SHIFTSWDE_ST_WIDE_MID_SHIFT # 4 SWDE_SW_S_SCALESWDE_ST_WIDE_SIDE_SCALE $ 4 SWDE_SW_S_SHIFTSWDE_ST_WIDE_SIDE_SHIFT % 8 SWDE_DE_M_F1_B0SWDE_D_ENH_MID_FILT_1_B0 & 8 SWDE_DE_M_F1_B1SWDE_D_ENH_MID_FILT_1_B1 ' 8 SWDE_DE_M_F1_B2SWDE_D_ENH_MID_FILT_1_B2 ( < SWDE_DE_M_F1_MA1 SWDE_D_ENH_MID_FILT_1_MA1 ) < SWDE_DE_M_F1_MA2 SWDE_D_ENH_MID_FILT_1_MA2 * 8 SWDE_DE_M_F2_B0SWDE_D_ENH_MID_FILT_2_B0 + 8 SWDE_DE_M_F2_B1SWDE_D_ENH_MID_FILT_2_B1 , 8 SWDE_DE_M_F2_B2SWDE_D_ENH_MID_FILT_2_B2 - < SWDE_DE_M_F2_MA1 SWDE_D_ENH_MID_FILT_2_MA1 . < SWDE_DE_M_F2_MA2 SWDE_D_ENH_MID_FILT_2_MA2 / 8 SWDE_DE_M_F3_B0SWDE_D_ENH_MID_FILT_3_B0 0 8 SWDE_DE_M_F3_B1SWDE_D_ENH_MID_FILT_3_B1 1 8 SWDE_DE_M_F3_B2SWDE_D_ENH_MID_FILT_3_B2 2 < SWDE_DE_M_F3_MA1 SWDE_D_ENH_MID_FILT_3_MA1 3 < SWDE_DE_M_F3_MA2 SWDE_D_ENH_MID_FILT_3_MA2 4 8 SWDE_DE_S_F1_B0SWDE_D_ENH_SIDE_FILT_1_B0 5 8 SWDE_DE_S_F1_B1SWDE_D_ENH_SIDE_FILT_1_B1 6 8 SWDE_DE_S_F1_B2SWDE_D_ENH_SIDE_FILT_1_B2 7 < SWDE_DE_S_F1_MA1 SWDE_D_ENH_SIDE_FILT_1_MA1 8 < SWDE_DE_S_F1_MA2 SWDE_D_ENH_SIDE_FILT_1_MA2 9 8 SWDE_DE_S_F2_B0SWDE_D_ENH_SIDE_FILT_2_B0 : 8 SWDE_DE_S_F2_B1SWDE_D_ENH_SIDE_FILT_2_B1 ; 8 SWDE_DE_S_F2_B2SWDE_D_ENH_SIDE_FILT_2_B2 < < SWDE_DE_S_F2_MA1 SWDE_D_ENH_SIDE_FILT_2_MA1 = < SWDE_DE_S_F2_MA2 SWDE_D_ENH_SIDE_FILT_2_MA2 > 8 SWDE_DE_S_F3_B0SWDE_D_ENH_SIDE_FILT_3_B0 ? 8 SWDE_DE_S_F3_B1SWDE_D_ENH_SIDE_FILT_3_B1 @ 8 SWDE_DE_S_F3_B2SWDE_D_ENH_SIDE_FILT_3_B2 A < SWDE_DE_S_v3_MA1 SWDE_D_ENH_SIDE_FILT_3_MA1 B < SWDE_DE_S_F3_MA2 SWDE_D_ENH_SIDE_FILT_3_MA2 C 4 SWDE_DE_M_SCALESWDE_D_ENH_MID_SCALE D 4 SWDE_DE_M_SHIFTSWDE_D_ENH_MID_SHIFT E 4 SWDE_DE_S_SCALESWDE_D_ENH_SIDE_SCALE F 4 SWDE_DE_S_SHIFTSWDE_D_ENH_SIDE_SHIFT I 0 SWDE_XFADE_BAL SWDE_SWDE_BALANCE � /� SHARED_PATCHING_STRUCTURE P SPTCH_MD_SLW_FRM -SHARED_PATCHING_STRUCTURE_MBDRC_SLEW_N_FRAMES